The present invention relates generally to a semiconductor chip and a semiconductor package including the same, and more particularly, to a semiconductor chip having through-silicon vias and a semiconductor package including the same.
In the semiconductor industry, packaging technologies for integrated circuits are continuously being developed to satisfy the demand toward miniaturization and mounting reliability. For example, the demand toward miniaturization has resulted in the development of techniques for implementing a package with a size approaching that of a chip, and the demand toward mounting reliability has highlighted the importance of packaging techniques for improving the efficiency of mounting work and mechanical and electrical reliability after mounting.
The term “stack” when referred to in the semiconductor industry means to vertically arrange at least two chips or packages. When taking advantage of stacking technology, it is possible to realize a product whose memory capacity is greater than that obtainable solely through semiconductor integration processes, and mounting area utilization efficiency can also be improved.
Stacking technologies are generally divided into a method of stacking individual semiconductor chips and simultaneously packaging the stacked semiconductor chips, and a method of stacking individually packaged semiconductor chips.
In stack packages, examples of bonding methods include a bonding method using metal wires and a bonding method using through-silicon vias (TSVs). Stack packages using the through-silicon vias are considered to overcome certain problems caused in stack packages using metal wires.
When compared to a stack package using metal wires, a stack package in which electrical connections are formed by through-silicon vias is capable of: preventing certain electrical degradation of the stack package, increasing operating speed, and achieving a higher level of miniaturization.
The electrical connections between stacked semiconductor chips are formed by the medium of junction metals which are interposed between exposed portions of through-silicon vias protruding from the lower surface of an upper semiconductor chip and the upper pads of a lower semiconductor chip. The junction metals can include, for example, solders.
However, in the course of electrically connecting the stacked semiconductor chips, unwanted portions of the upper semiconductor chip and the lower semiconductor chip may become electrically short-circuited, whereby electrical short circuits frequently occur.
In more detail, semiconductor chips having through-silicon vias include upper pads that are electrically and physically attached to each other by the medium of the junction metals and a filler material.
The exposed portions of the through-silicon vias of the upper semiconductor chip and the upper pads of the lower semiconductor chip are electrically connected to each other by melting the junction metals interposed therebetween through a reflow process.
When conducting the reflow process, the melted junction metals are likely to flow onto the lower surface of the upper semiconductor chip along the exposed portions of the through-silicon vias, so that the unwanted portions of the upper semiconductor chip and the lower semiconductor chip are electrically short-circuited, whereby electrical short circuits frequently occur. If the short circuits occur, misoperation of the semiconductor chip is caused, whereby the manufacturing yield can markedly decrease.
While a process for applying an insulating material to the lower surface of the semiconductor chip can be additionally conducted to prevent the occurrence of a short circuit, processing difficulties are caused when attempting to apply the insulation material only to the lower surface of the semiconductor chip while exposing the electrically connected portions, and the processing time and processing cost increase.